1. Field of the Invention
The present invention relates to a protective arrangement for MOS circuits (insulated-gate field-effect transistor integrated circuites) which lies between a pad on an insulating layer covering the substrate of the MOS circuit and a transistor to be protected, which pad contains a resistor of the opposite conductivity type, and which resistor is incorporated in the substrate and which connects the pad to a terminal of the transistor.
2. Description of the Prior Art
Protective arrangements have been used since the early times of MOS integrated circuits to protect the sensitive gate insulating layer of the MOS device from static and/or dynamic overvoltages which reach the pad and, thus, the gate of the associated transistor via the external terminals of a packaged integrated circuit. If the dielectric strength of the gate insulating layer is exceeded, the gate insulating layer could be destroyed. The prior art is described, for example, in Kubo, "Breakdown Preventing Circuit and an Integrated Device Thereof for a Semiconductor Device Having an Insulate Gate Electrode," U.S. Pat. No. 3,590,340. If necessary, a bypass transistor may be connected to the junction between the resistor and the transistor to be protected.
It turned out, however, that the insertion of a resistor between the pad and the transistor to be protected and the use of a bypass transistor are not sufficient. Further steps are necessary to ensure that the arrangement serves its purpose if the integrated circuits are to pass the curent standard test, in which a voltage pulse of the order of 2 kV, which can cause a pulsed current of the order of 1A, is applied from a capacitor through a series resistor to a pad.
The object of the invention as claimed is to improve the prior art protective arrangement in such a way that it reliably protects the transistors coupled to the pad of a MOS integrated circuit, at least at the above test values.